This invention relates to a semiconductor device constituted by an ultra high frequency GaAs field effect transistor.
Previously known semiconductor devices including an ultra high frequency GaAs field effect transistor (hereinafter referred to as GaAs FET) have the device structure as shown in FIG. 1, for example. More specifically, a lightly doped semiconductor layer 2 of an N conduction type is formed on a semi-insulating undoped GaAs substrate 1 (hereinafter referred to as GaAs substrate). Heavily doped regions 3a and 3b constituting a source and drain, respectively are formed in the predetermined region of the lightly doped (low impurity concentration) layer 2 with a predetermined interval therebetween. A gate electrode 4 is formed on the lightly doped semiconductor layer 2 between the heavily doped regions 3a and 3b, and is made of metal such as Al, Au, etc. or is made of stacking metal layers such as Ti, Al. Source/drain extraction electrodes 5a and 5b of Au Ge/Pt, etc. are formed on the heavily doped regions 3a and 3b, respectively.
This conventional semiconductor device 10 is manufactured as follows.
First, as shown in FIG. 2A, the N conduction type lightly doped semiconductor layer 2 which acts as an active layer is selectively formed on the GaAs substrate 1. An SiO.sub.2 film is formed on the lightly doped semiconductor layer 2, and the SiO.sub.2 film thus formed is selectively etched to form a dummy gate 11 having a predetermined pattern. A side wall film constituting member 12 of a Si.sub.3 N.sub.4 film is deposited so as to cover the dummy gate 11.
As shown in FIG. 2B, a resist film (not shown) is formed on the side wall constituting member 12. The resist film is etched-back to be flattened through a reactive ion etching technique (hereinafter referred to as RIE), thus removing the side wall film constituting member 12 portion on the dummy gate 11. Using, as a mask, the dummy gate 11 and the portion of the side wall film constituting member 12 at the side thereof, impurities of Si are ion-implanted in the lightly doped semiconductor layer 2 through the side wall film constituting member 12 portions on the lightly doped semiconductor layer 2. The implanted impurities are activated to form the heavily doped regions 3a and 3b.
As shown in FIG. 2C, the dummy gate 11 is removed through wet etching using NH.sub.4 F, for example.
As shown in FIG. 2D, an electrode constituting member 13 of metal such as Al, Au or stacking metal layers such as Ti, Al thereof is formed on the exposed surface of the lightly doped layer 2 using the remaining side wall film constituting member 12 as a mask.
As shown in FIG. 2E, both the side wall film constituting member 12 and the electrode constituting member 13 thereon are simultaneously removed through a chemical dry etching technique (CDE) so as to form a gate electrode 14 having a predetermined pattern on the lightly doped semiconductor layer 2.
Finally, as shown in FIG. 2F, an ohmic contact is patterned on the heavily doped regions 3a and 3b to form a resist pattern and an ohmic metal contact of AuGe/Pt, etc. is deposited by, e.g., evaporation, etc. After that, the source/drain extraction electrodes 5a and 5b are formed by means of a tape lift-off technique, thus completing the semiconductor device 10 by alloying the ohmic metal contact.
The conventional semiconductor device as shown in FIG. 1 has the following problems.
(1) The heavily doped regions 3a and 3b and the source/drain extraction electrodes 5a and 5b are not self-aligned with each other so that the interval between the gate electrode 4 and the extraction electrode 5a is larger than that between the gate electrode 4 and the heavily doped region 3a. This leads to insufficient reduction of a so-called source resistance Rs and large variations therein. As a result, the semiconductor device 10 cannot have a good high frequency performance.
(2) The intervals between the gate electrode 4 and the source/drain extraction electrodes 5a and 5b cannot be sufficiently reduced. Thus, the device cannot be sufficiently miniaturized and so its integration degree cannot also be sufficiently enhanced.
(3) The gate electrode 4 and the source/drain extraction electrodes 5a, 5b are made of different materials so that manufacturing process of the device is complicated.
(4) The ohmic property of the source/drain extraction electrodes is improved through the alloying of AuGe. However, if it is intended to further improve the ohmic property by increasing the concentration of Ge, a so-called ball-up phenomenon that the extraction electrodes 5a and 5b are peeled off will occur. If the extraction electrodes 5a and 5b are made of stacking metal layerssuch as AuGe, Pt, etc. as a holding member in order to prevent the aforesaid phenomenon, the electrode structure becomes complicated still more.
Further, the aforesaid method for manufacturing the semiconductor device, as shown in FIGS. 2A to 2F has the following problems.
(1) The heavily doped regions 3a and 3b, which act as a source and a drain, respectively, cannot have a sffficiently high impurity concentration and also the gate is in a Schottky gate structure so that in order to improve the ohmic property of the source/drain extraction electrodes 5a and 5b, the gate electrode 14 and the electrodes 5a, 5b must be made of different materials, thus making the manufacturing process complicated.
(2) The ohmic property of the source/drain extraction electrodes 5a and 5b can be improved by increasing the Ge concentration in the AuGe alloy constituting an ohmic metal contact. If the Ge concentration is increased, however, a so-called ball-up phenomenon that the extraction electrodes are peel off will occur. The provision of the extraction electrodes 5a and 5b in order to prevent such a phenomenon as a holding member of stacking metal layers such as Pt, Ni, Au, etc. makes the manufacturing process complicated.
(3) The heavily doped regions 3a and 3b are not self-aligned with the extraction electrodes 5a, 5b. This makes the so-called mask alignment process, etc. complicated and makes the completion of the miniaturized semiconductor device difficult.
(4) In order to improve the ohmic property of the source/drain extraction electrodes 5a and- 5b, the alloyed process of forming the ohmic metal contact of AuGe is required.
(5) The ohmic metal contact formed by the alloying process is liable to be influenced by physical and chemical conditions. Therefore, the selection of the kind of chemicals which are required for the succeeding treatment processes, and of time and temperature conditions in the processes is difficult.